Workshop on Machine Learning for Hardware Design and Optimization

Monday, August 1, 2022  1:00 – 4:00 PM. In Person

6280 America Center Dr., San Jose, California



Learn how industry and academia can work together successfully to apply machine learning algorithms to advance the efficiency and quality of microelectronics design

In April 2022, CAEML received a second 5-year award from the National Science Foundation. This workshop will provide an opportunity for CAEML faculty to present research accomplishments and the agenda for upcoming research to their industry peers in Silicon Valley. Speakers include representatives of CAEML member companies who will share how the center’s research has improved their productivity.


12:30 PM             Doors open for check-in

1:00 PM               Elyse Rosenbaum (Illinois): Brief Introduction to CAEML and Overview of Workshop

1:10 PM               Madhavan Swaminathan (Georgia Tech): Machine Learning for the Design of Micro Electronic Systems

 1:40 PM              Chris Cheng (HPE): CAEML Phase I Collaboration

1:50 PM               Aydin Aysu (NC State): Deus Ex Machina: Learning Techniques for Breakthrough in Side-Channel Security Assessment of Integrated Circuits

2:15 PM               Huan Yu (Georgia Tech & Industry): A Ph.D. Student’s Impression of CAEML

2:25 PM               BREAK

2:35 PM               Paul Franzon (NC State): Generative Adversarial Networks for Model Building

2:55 PM               Biliana Paskaleva (Sandia): Can you teach new tricks (circuits) to an old dog? AI & ML Beyond Cat Pictures

3:05 PM               Elyse Rosenbaum: Neural Network Dynamical Models of Circuits: Merits and Pitfalls

3:25 PM               Sung Kyu Lim (Georgia Tech): Physical Design Tool Parameter Auto-Tuning with   Machine Learning

3:45 PM               Elyse Rosenbaum: NSF’s IUCRC program and CAEML Operations

3:55 PM               Q&A

The workshop will double as a new member recruitment event and, as such, it is open to employees of companies that are not CAEML members . Non-members will have an opportunity to learn about the center and consider whether membership is of interest. Engineers from the member companies will also be warmly welcomed, especially those who were unable to interact in-person with the university researchers the past two years due to pandemic travel restrictions.

Advance registration is required; the registration form can be found here .

Prospective attendees may wish to check out some recent articles about CAEML:

CAEML extends its appreciation to Hewlett Packard Enterprise for providing the workshop space.

Workshop Presenters

Aydin Aysu is currently an assistant professor and Bennett Faculty Fellow at the Electrical and Computer Engineering Department of North Carolina State University, where he leads HECTOR: Hardware Cybersecurity Research Lab.  He got his M.S from Sabanci University in Istanbul, Turkey, and his Ph.D. from Virginia Tech. Before joining NC State, he was a post-doctoral researcher at the University of Texas at Austin.  Dr. Aysu's interests are broadly in hardware security research and cybersecurity education.  He has won the 2019 NC State Faculty Development Award, 2019 NSF Research Initiative (CRII) award, the 2020 Bennett Faculty award, the 2020 NSF CAREER award, and the 2022 Google Research Scholar award.  His papers have won the best paper runner-up awards at 2018, 2019, and 2022 IEEE HOST conferences, and the best paper award at 2019 GLS-VLSI and 2020 DATE conferences, and an IEEE CEDA top pick paper award in hardware security between 2015--2020.  He is an IEEE senior member

Chris Cheng is a Distinguished Technologist at the Storage Division of Hewlett-Packard Enterprise. He is responsible for managing all high speed, analog/mixed signal designs and hardware machine learning development within the Storage Division. He also held senior engineering positions in Sun Microsystems where he developed the original GTL system bus with Bill Gunning. He was a Principal Engineer in Intel where he led high speed processor bus design team. He was the first hardware engineer in 3PAR and guided their high-speed design effort until it was acquired by Hewlett Packard.

Paul D. Franzon is currently the Cirrus Logic Distinguished Professor and the Director of Graduate programs in the Department of Electrical and Computer Engineering at North Carolina State University.  He earned his Ph.D. from the University of Adelaide, Adelaide, Australia.  He has also worked at AT&T Bell Laboratories, DSTO Australia, Australia Telecom, Rambus, and four companies he cofounded, Communica, LightSpin Technologies, Polymer Braille Inc. and Indago Technologies.  His current interests include applying machine learning to EDA, building AI accelerators, RFID, advanced packaging, 2.5D and 3DICs and secure chip design. He has lead several major efforts and published over 300 papers in these areas.  In 1993 he received an NSF Young Investigators Award, in 2001 was selected to join the NCSU Academy of Outstanding Teachers, in 2003, selected as a Distinguished Undergraduate Alumni Professor, received the Alcoa Research Award in 2005, the Board of Governors Teaching Award in 2014, and the Distinguished Graduate Alumni Professor in 2021.  He has been awarded faculty awards from Qualcomm, IBM and Google.  He served with the Australian Army Reserve for 13 years as an Infantry Soldier and Officer.  He is a Fellow of the IEEE.

Sung Kyu Lim received Ph.D. degree from UCLA in 2000. He joined the School of Electrical and Computer Engineering at the Georgia Institute of Technology in 2001, where he is currently Motorola Solutions Foundation Professor. His research focus is on the architecture, design, and electronic design automation for 2.5D and 3D ICs using both the traditional and machine learning algorithms. He has published more than 400 papers on the topics. He received the Best Paper Award from the IEEE Transactions on Electromagnetic Compatibility and the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems in 2022.

Biliana S. Paskaleva is a Principal member of the Technical Staff at the Component and System Analysis department at Sandia National  Laboratories. Biliana earned B.S. in Electrical Engineering in 1992 from the Technical University in Varna, Bulgaria, and PhD in Electrical and Computer Engineering from the University of New Mexico in 2009. Biliana joined Sandia in 2006 as a graduate student intern and became a Senior Member of Technical Staff in 2010. From 2006 to 2018, Biliana worked as device and circuit analyst for the Qualification Alternative for Sandia Pulsed Reactor (QASPR) program. Biliana was a recipient and team representative of the 2017 SNL National Nuclear Security  Administration Defense Programs Awards of Excellence for the work on the QASPR survey simulations for the W88 ALT370 Team. Currently,  Biliana is Principal investigator and technical lead for several projects at Sandia National Laboratories funded through the Radiation Effects &  High Energy Density Science Research Foundation Laboratory Directed Research & Development program, Nuclear survivability engineering  campaign, and the Advanced scientific computing programBiliana's interests include development of data-driven and machine learning  approaches for modeling of semiconductor devices and circuits; verification and validation, and uncertainty quantification (UQ), development and application of multi-resolution, multi-fidelity, and/or reduced-order modeling and UQ characterization and propagation approaches for  integrated electrical systems.

Elyse Rosenbaum is the Melvin and Anne Louise Hassebrock Professor in Electrical and Computer Engineering at the University of Illinois Urbana-Champaign. She received the Ph.D. degree in electrical engineering from the University of California, Berkeley. She is the director of the NSF-supported Center for Advanced Electronics through Machine Learning (CAEML), a joint project of the University of Illinois, Georgia Tech and North Carolina State University. Her current research interests include machine-learning aided behavioral modeling of microelectronic components and systems, compact models, circuit reliability simulation, component and system-level ESD reliability, and ESD-robust high-speed I/O circuit design.

Dr. Rosenbaum has authored or co-authored about 200 technical papers; she has been an editor for IEEE Transactions on Device and Materials Reliability and IEEE Transactions on Electron Devices. She was the recipient of a Best Student Paper Award from the IEDM, Outstanding Paper Award and 2 Best Paper Awards from the EOS/ESD Symposium, a Technical Excellence Award from the SRC, an NSF CAREER award, an IBM Faculty Award, and the ESD Association’s Industry Pioneer Recognition Award. She is a Fellow of the IEEE.

Madhavan Swaminathan is the John Pippin Chair in Microsystems Packaging & Electromagnetics in the School of Electrical and Computer Engineering (ECE), Professor in ECE with a joint appointment in the School of Materials Science and Engineering (MSE), and Director of the 3D Systems Packaging Research Center (PRC), Georgia Tech (GT) ( He also serves as the Site Director for the NSF Center for Advanced Electronics through Machine Learning (CAEML: and Theme Leader for Heterogeneous Integration, at the SRC JUMP ASCENT Center ( Prior to joining GT, he was with IBM working on packaging for supercomputers.

He is the author of 550+ refereed technical publications and holds 31 patents. He is the primary author and co-editor of 3 books and 5 book chapters, founder and co-founder of two start-up companies, and founder of the IEEE Conference on Electrical Design of Advanced Packaging and Systems (EDAPS), a premier conference sponsored by the IEEE Electronics Packaging Society (EPS). He is an IEEE Fellow and has served as the Distinguished Lecturer for the IEEE Electromagnetic Compatibility (EMC) society.

He received his MS and PhD degrees in Electrical Engineering from Syracuse University in 1989 and 1991, respectively.

Huan Yu is a signal integrity engineer at Apple. He received his Ph.D. degree in electrical and computer engineering from Georgia Institute of  Technology in 2019. He is a former PhD student with CAEML. His research interests include electronics modeling, simulation and optimization, with a focus on Machine Learning.



Fall 2022 Semiannual Meeting scheduled for November 9 & 10 at Illinois

Please mark your calendar for November 9 & 10 and plan to join us at Illinois for the CAEML Fall 2022 Semiannual Meeting. Information about registration and the agenda will be sent to member company contacts later in the year.

Any companies considering membership and wishing to be a guest at the meeting can contact Center Operations Manager Jill Peckham at or 217-265-5292 for more information on the center, its research and meeting attendance options.


Recordings of past webinars are available to Center members on the CAEML Repository.

December 13, 2021  Rhett Davis NC State:  PPA Modeling and Optimization with Transfer Learning and Evolutionary Algorithms

September 23, 2021  Archit Gajjar NC State University   FPGA Hardware Accelerator for Real Time Security

June 9, 2021  Jie Xiong  Recurrent Neural Network Models for Efficient Simulation of Circuit Aging and Stochastic Effects

May 25, 2021  Luis Francisco A Machine Learning Based Design Rule Checker

May 18, 2021  Joshua Hanson Expressiveness and generalizability of recurrent neural networks for systems modeling

May 4, 2021 Xu Chen Machine Learning and Uncertainty Quantification Methods for Hardware Design

March 22, 2021 Aydin Aysu, Priyank Kashyap and Furkin Aydin Deus Ex Machina

December 10, 2020 Majid Ahadi High-speed Channel Analysis and Design with Machine Learning

November 18, 2020 Yu Zhou Time Series Prediction Using Deep Markov Models

July 21, 2020 Alan Yank Model-Augmented Estimation of Condition Mutual Information for Feature Selection

July 10, 2020 Paul Franzon Candidate Algorithms for Mixed RF and Circuit Design

June 24, 2020 Hakki Torun & Madhavan Swaminathan Demystifying ML

March 20, 2020 Anthony Agnesina Introduction to ML-based FPGA Compilation

August 12, 2019 Aydin Aysu & Arjit Raychowdhury Deep Learning Based Side-Channel Attacks

April 3, 2019 Xu Chen Modeling of Electrical Circuits with Recurrent Neural Networks

February 25, 2019 Bowen Li Behavioral Model Development for High Speed Links

February 12, 2019 Paul Franzon Surrogate Modeling & Bayesian Optimization

September 19, 2018 Madhavan Swaminathan ML Techniques for Packaging Problems

August 17, 2017 Weiyi Qi  Machine Learning Assisted IC Design Modeling, Optimization and IP Reuse