Coordinated Science Laboratory
Center for Advanced Electronics Through Machine Learning

Current Research Projects

Siamese Graph Neural Networks for Finding Circuit Graph Isomorphisms

The Circuit Graph Isomorphism (CGI) problem is a fundamental computational problem in Electronic Design Automation (EDA) that involves determining the equivalence of two circuit graphs. Given two circuit graphs, the challenge is to establish whether they are isomorphic, meaning that they have the same structure but with different labels assigned to their nodes and edges. As a fundamental NP-complete problem, the CGI issue arises frequently in EDA and has been the focus of extensive research in the past. A solution to this problem would have significant implications for the design process, enabling a faster and more efficient design flow.

  • Project PI: Paul Franzon
  • Project Timeline: January 1, 2024 - August 2026

ML-based Generation of Fine-grained TSV Models for Power Integrity Analysis

The goal of this project is to develop ML algorithms to automatically create fine-grained TSV models, which are used to study current crowding inside a TSV and its impact on effective resistance. These models are deployed to calculate IR-drop and least resistive paths in full-chip power delivery network for 3D and 2.5D ICs.

  • Project PI: Sung Kyu Lim
  • Project Timeline: January 1, 2024 - June 30, 2026

Uncertainty-Aware Parametric Behavioral Modeling of Circuit Devices

This project proposes to investigate the potential of neural operator techniques for developing parameterized, compact models that describe the behavior of circuit components. Neural operators, an emerging tool in scientific computing, utilize machine learning algorithms to identify nonlinear relationships within functional spaces. This approach represents an advancement over traditional machine learning surrogate models, such as neural networks and Gaussian process regression, by providing a framework for constructing models that operate in continuous time and are invariant to time
discretization.

  • Project PI: Xu Chen
  • Project Timeline: August 15, 2024 - August 14, 2026

AI/ML Assisted Design and Uncertainty Quantification for High-Performance Heterogeneous Integration with Co-Packaged Optics

The goal of this project is to increase the overall efficiency of 2.5D/3D heterogeneous integration with advanced co-packaged photonics and to quantify uncertainty through Bayesian learning for deep co-design methods. Through a robust optimization process, this framework will provide the best design choices at an early stage in the design cycle.

  • Project PI: Madhavan Swaminathan
  • Project Timeline: August 15, 2024 - August 14, 2026

Natural Language Optimization of Interconnect Problems Using Multimodal LLM for PCBs and Analog Integrated Circuits

The project's goals are to (1) fine tune an LLM to solve signal integrity problems in PCB and on-chip routing using a natural language interface, and (2) demonstrate the potential of using and generating multimodal information, e.g. eye diagrams and frequency plots.

  • Project PI: Paul Franzon
  • Project Co-Is: C-W Wong & Tianfu Wu 
  • Project Timeline: August 15, 2024 - August 14, 2026

Power MOSFET Design Automation via Invertible Neural Network

This project aims to replace the TCAD simulator with an invertible neural network. The forward model may be used for device design optimization, a task for which the slow TCAD simulator is not well suited. The inverse model will be used for automated device design (“synthesis”) based on performance specifications.

  • Project PI: Elyse Rosenbaum
  • Project Timeline: August 15, 2024 - August 14, 2026

Detecting and Mitigating Fault Injection Attacks on AI/ML Chiplets

This project can expose potential fault injection vulnerabilities in member companies’ systems that use AI/ML hardware (chiplets) – such vulnerabilities can lead to intellectual property theft or critical errors in AI/ML output.  Then, the project can address the vulnerabilities found by building more resilient solutions without replacing the hardware.   

  • Project PI: Aydin Aysu
  • Project Timeline: January 1, 2025 - December 31, 2026

Reinforcement Learning and Test-Time Scaling for Continuously Training and Improving LLMs for Analog/Mixed-Signal Circuit Design

This project aims to provide a secure, organization-specific LLM pipeline tailored for analog/mixed-signal (AMS) circuit design.  Collectively, this project will reduce design cycles, preserve institutional knowledge, boost designer productivity, improve accuracy, and drive the future of AI-assisted AMS design automation.

  • Project PI: Bin Hu 
  • Project Co-Is: Pavan Hanumolu, Elyse Rosenbaum, and Huan Zhan
  • Project Timeline: August 1, 2025 - July 31, 2027

Deep Learning for End-to-End Time-Domain Analysis

The proposed conditional generative model based end-to-end time-domain SI analysis will enable thorough optimization of I/O drivers and equalization settings in a fast, accurate and reliable manner. This will provide various opportunities for improving I/O performance and equalization design that result in better SI for increased data rates along with reduced design re-spins and design closure times. 

  • Project PI: Madhavan Swaminathan
  • Project Timeline: August 1, 2025 - July 31, 2027

Surrogate Optimization of Temperature and Stress in Heterogeneously Integrated Microsystems

This project will create a reusable public framework for multi-objective optimization of IP block selection and placement with thermomechanical constraints in HI microsystems. This framework applies the surrogate optimization approach used in past CAEML efforts to reduce the number of time-consuming simulations while maintaining high accuracy for critical outcomes.

  • Project PI: Rhett Davis
  • Project Co-I: Mansoor Haider
  • Project Timeline: August 1, 2025 - July 31, 2027

Applying Symbolic Regression to Problems in Package and Circuit Design

This project’s goal is to demonstrate and leverage Symbolic Regression (SR) as a basis for modeling complex, multi-faceted EDA problems.  This project will benchmark the ability of symbolic regression techniques to fit mathematical functions to common problems in SI, PI, thermal management, and analog and SerDes designs, and demonstrate the applications of this modeling for real-world designs. 

  • Project PI: Paul Franzon
  • Project Timeline: August 1, 2025 - July 31, 2027

Machine Learning Design for 3D Optical Interconnects

This project will explore the emerging direction in panel scale optical interconnects for large scale AI computing.   The goal of this project is to address power, performance, area (PPA) in the context of optical routing for complex systems employing 100+ chiplets on a single large substrate.  This project extends the use of photonics into the substrate with a focus on optical routing as opposed to bringing data over fiber into the substrate, with the rest of the communication in the substrate being electrical.  

  • Project PI: Ning Li
  • Project Timeline: January 1, 2026 - December 31, 2027