Coordinated Science Laboratory
Center for Advanced Electronics Through Machine Learning

Current Research Projects

Security Analysis of XG Boost Ransomware Detector through Side-Channel Attacks and/or Power Hammering Attacks

The proposed research will be conducted over three phases. Phase 1: Collect relevant datasets for different classification problems and devise an experimental setup to conduct experiments. Phase 2: Attacking FPGA with side-channel attacks to steal the model information and/or derange the FPGA by power-hammering attacks. Phase 3: Innovate techniques to defend against such attacks.  

  • Project PI: Paul Franzon & Aydin Aysu
  • Project Timeline: August 1, 2022 - December 31, 2024

IC Failures-In-Time (FIT) Rate Prediction. Part 1: MOL and BEOL Time Dependent Dielectric Breakdown

This project will demonstrate physics-integrated variational autoencoders that generate time-to-breakdown distributions of BEOL and MOL dielectrics with variable areas. The key impediment to a purely physics-based approach is that the underlying distribution of dielectric thicknesses is not known.

  • Project PI: Elyse Rosenbaum
  • Project Timeline: August 1, 2022 - December 31, 2024

Quantifying Privacy in Distributed Learning for Integrated Circuit Design

This project seeks to promote the sharing of proprietary data in collaborative databases by experimentally quantifying the privacy of distributed learning on an integrated circuit design application. This project will set up a distributed database with an ML-EDA application, show that deterministic privacy when granting access can be guaranteed by an approach called View-Verified Data Exchange, and show that differential privacy in Federated Learning can be guaranteed by a model-poisoning defense.

  • Project PIs: Rhett Davis, Rada Chirkova, Bo Li
  • Project Timeline: January 1, 2023 - December 31, 2024

Physical Design Parameter Optimization (PDPO) Using Reinforcement Learning

Given a synthesized netlist, PPA targets, a target technology, and the list of PD tool parameters, the objective of this project is to (1) tune the parameters automatically using Reinforcement Learning (RL) models so that the final GDS layouts meet the PPA goals, and (2) minimize the time needed to train the RL model.

  • Project PI: Sung Kyu Lim
  • Project Timeline: January 1, 2023 - December 31, 2024

Signal Integrity Aware GAIL Routers for PCBs

Today's auto routers split the routing into two phases and rely on handcrafted heuristics to guide the routing.  Through this project, we plan to create an approach to routing that can apply to breakout, DDR, and HBM routing while ensuring optimal signal integrity performances across different design rules.

  • Project PI: Paul Franzon
  • Project Timeline: August 15, 2023 - August 14, 2025

Transfer Learning Framework 

Development of transfer Learning Framework to deploy pre trained machine learning model for training of new model having similar behavior.  This will reduce the number of training samples and increase the accuracy of the new ML model. 

  • Project PI: Madhavan Swaminathan
  • Project Timeline: August 15, 2023 - August 14, 2025

Variation Aware Analog Design Mentor

This projects seeks to develop human interface, evaluate if the design mentor improves the efficiency of inexperienced designers, and evaluate faster algorithms for calculating Shapley values.  Other milestones include creating an AI mentor that assists and designer to formulate a circuit design with low sensitivity to process variations.  Also, quantify whether the design mentor's outputs are significantly affected by the use of the netlists that are extracted from layout.  

  • Project PI: Elyse Rosenbaum 
  • Project Timeline: August 15, 2023 - August 14, 2025

Bayesian ML for Reliable Ferroelectric In-Memory Computing

This projects addresses optimized, and reliable design of intelligent autonomous microsystems based on emerging device technologies through Bayesian learning approaches.  The project is in synergy with multiple programs on probabilistic AI like SNL's COINFLIPS project.

  • Project PIs: Abhronil Sengupta & Madhavan Swaminathan
  • Project Timeline: August 15, 2023 - August 14, 2025

Siamese Graph Neural Networks for Finding Circuit Graph Isomorphisms

The Circuit Graph Isomorphism (CGI) problem is a fundamental computational problem in Electronic Design Automation (EDA) that involves determining the equivalence of two circuit graphs. Given two circuit graphs, the challenge is to establish whether they are isomorphic, meaning that they have the same structure but with different labels assigned to their nodes and edges. As a fundamental NP-complete problem, the CGI issue arises frequently in EDA and has been the focus of extensive research in the past. A solution to this problem would have significant implications for the design process, enabling a faster and more efficient design flow.

  • Project PI: Paul Franzon
  • Project Timeline: January 1, 2024 - December 31, 2025

ML-based Generation of Fine-grained TSV Models for Power Integrity Analysis

The goal of this project is to develop ML algorithms to automatically create fine-grained TSV models, which are used to study current crowding inside a TSV and its impact on effective resistance. These models are deployed to calculate IR-drop and least resistive paths in full-chip power delivery network for 3D and 2.5D ICs.

  • Project PI: Sung Kyu Lim
  • Project Timeline: January 1, 2024 - December 31, 2025

Uncertainty-Aware Parametric Behavioral Modeling of Circuit Devices

This project proposes to investigate the potential of neural operator techniques for developing parameterized, compact models that describe the behavior of circuit components. Neural operators, an emerging tool in scientific computing, utilize machine learning algorithms to identify nonlinear relationships within functional spaces. This approach represents an advancement over traditional machine learning surrogate models, such as neural networks and Gaussian process regression, by providing a framework for constructing models that operate in continuous time and are invariant to time
discretization.

  • Project PI: Xu Chen
  • Project Timeline: August 15, 2024 - August 14, 2026

AI/ML Assisted Design and Uncertainty Quantification for High-Performance Heterogeneous Integration with Co-Packaged Optics

The goal of this project is to increase the overall efficiency of 2.5D/3D heterogeneous integration with advanced co-packaged photonics and to quantify uncertainty through Bayesian learning for deep co-design methods. Through a robust optimization process, this framework will provide the best design choices at an early stage in the design cycle.

  • Project PI: Madhavan Swaminathan
  • Project Timeline: August 15, 2024 - August 14, 2026

Natural Language Optimization of Interconnect Problems Using Multimodal LLM for PCBs and Analog Integrated Circuits

The project's goals are to (1) fine tune an LLM to solve signal integrity problems in PCB and on-chip routing using a natural language interface, and (2) demonstrate the potential of using and generating multimodal information, e.g. eye diagrams and frequency plots.

  • Project PI: Paul Franzon
  • Project Co-Is: C-W Wong & Tianfu Wu 
  • Project Timeline: August 15, 2024 - August 14, 2026

Power MOSFET Design Automation via Invertible Neural Network

This project aims to replace the TCAD simulator with an invertible neural network. The forward model may be used for device design optimization, a task for which the slow TCAD simulator is not well suited. The inverse model will be used for automated device design (“synthesis”) based on performance specifications.

  • Project PI: Elyse Rosenbaum
  • Project Timeline: August 15, 2024 - August 14, 2026