Current Research Projects

NL2PPA: Netlist-to-PPA Prediction Using Machine Learning

This project aims to build machine learning models and develop associated tools to predict PPA (power/performance/area) given an RTL description of a circuit, eliminating the need to undertake the lengthy physical design process. Using the predicted PPA results, designers can fix and/or improve RTL in turn. The inputs to the model include the target technology specs (e.g., technology node, supply voltage, target frequency), netlist info (e.g., number of IPs/gates/nets, connectivity), physical design options (e.g., footprint, placement density, P&R algorithms, clock/power network options), and other key features that will help improve the prediction accuracy.

  • Project PI: Sungkyu Lim
  • Research Thrust: Design and System Optimization
  • Research timeline: January 1, 2019 – May 15, 2021

RNN Models for Computationally-Efficient Simulation of Circuit Aging Including Stochastic Effects

This project will develop a method for accurate and efficient simulation of circuit aging due to hot carrier injection (HCI) and bias temperature instability (BTI). For design-technology co-optimization (DTCO), the simulations must cover the range of use conditions, i.e., the “mission profile,” which includes the input vector, and both the deterministic and stochastic aspects of aging should be simulated. Each circuit block, i.e. library cell or IP block, will be represented by a limited-complexity black-box model, such as the RNN, that takes the circuit’s total operating time as one of its inputs. Ensuring the stability of each black-box model alone and when interconnected to other circuit models is a significant research challenge.

  • Project PIs:  Elyse Rosenbaum, Maxim Raginsky
  • Research Thrust: Modeling and Simulation; Reliability and Security
  • Research Timeline: January 1, 2019 to May 15, 2021

High-Speed Bus Physical Design Analysis through Machine Learning

This project will create a dynamic ML ecosystem to characterize electrical performance of each net in a given PCB/package layout file with confidence bounds and leverage pre-PD simulation to collect training data. The use of stochastic collocation to will be used to account for manufacturing tolerance and nets will be ranked in descending order of SI performance to determine any bottleneck in the system.

  • Project PIs: Xu Chen, Madhavan Swaminathan
  • Research Thrust: Design and System Optimization; Modeling and Simulation; Verification
  • Research Timeline Jan 1, 2019 – May 15, 2021

Enabling Side-Channel Attacks on Post-Quantum Protocols through Machine Learning

The primary purpose of this project is to enable single-trace power side-channel attacks on post-quantum key-exchange protocols using machine learning and to quantify the strength of timing obfuscation defenses against those attacks. The central question to be addressed is whether machine-learning classifiers provide stronger attacks compared to the conventional ones in the context of post-quantum cryptosystems, and to what extent can obfuscation methods hide the vulnerability.

  • Project PI: Aydin Aysu
  • Research Thrust: Reliability and Security
  • Research Timeline Jan 1, 2019 – May 15, 2021

Design Space Exploration Using DNN

Designing advanced semiconductor manufacturing process brings area, speed, power and other benefits but also new performance challenges as a result of the pure physics of running current through tiny wires. Often times there are post tape-out escapes both at the silicon and packaging levels due to inadequate analysis at an early design stage. This sometimes is due to lack of time or poor assumptions made by the designer which may be inaccurate. We address these challenges in this project by focusing on early Design Space Exploration (DSE). Such a solution we believe would be applicable to various levels in the system hierarchy.

  • Project PI: Madhavan Swaminathan
  • Research Thrust: Design and System Optimization; Reliability and Security
  • Research Timeline Jan 1, 2019 – May 15, 2021

FPGA Hardware Accelerator for Real Time Security

Determine design approaches to building real time detection systems for ransomware defenses, with a focus on Random Forest ML.  Investigate the training support needs as well.  Determine higher level ML approaches that support model update without redesign.

  • Project PI: Paul Franzon
  • Project Timeline: Jan 1, 2020 – Dec 31, 2021

Machine Learning Method for Inverse Design and Optimization of High-Speed Links

Our plan is to develop a machine learning-driven method for solving inverse and optimization problems in hardware design. We will leverage forward surrogate models developed in earlier CAEML research, along with additional training and dimensionality reduction methods to synthesize candidate designs that meet specified performance objects, speeding up the design process,

  • Project PI: Xu Chen and Andreas Cangellaris
  • Project Timeline: Jan 1, 2021 – July 31, 2022

High Dimensional Optimization and Inverse Methods for Electronic Design

This project aims to use high dimensional optimization approaches in electronic system design. Techniques that will be considered include surrogate modeling, Bayesian optimization, and inverse neural networks.

  • Project PI: Paul Franzon, Brian Floyd and Dror Baron
  • Project Timeline: Jan 1, 2021 – July 31, 2022

GAN generated models for Signal Integrity, Thermal Modeling, Etc.

This project will use conditional GANs to model drivers and receivers and to support thermal modeling.

  • Project PI: Paul Franzon, Chau -Wai Wu, Tainfu Wu, Rhett Davis & Dror Baron
  • Project Timeline: Jan 1, 2021 – July 31, 2022

ML-Based Security Analysis of Homomorphic Encryption Side-Channels

This project explores implementation security issues of homomorphic encryption solutions. Specifically, the project aims exposing the first side-channel vulnerabilities of edge devices executing homomorphic encryption/decryption and integrating the side-channel analysis into standard EDA flows. Machine learning techniques will enable automating the proposed work and achieving effective attacks that can outperform conventional ones

  • Project PI: Aydin Aysu and Paul Franzon
  • Project Timeline: Jan 1, 2021 – July 31, 2022

Reliability-Driven Thermal Optimization of 2.5D and 3D Packaging Architectures

There has been rapid development of new packaging technologies to support 2.5/3D heterogeneous integration. To fully exploit those capabilities without sacrificing time-to-market requires the development of a multi-objective optimization framework that can answer the following questions: What are the optimum architecture and materials from a set of possible choices? Given a fixed architecture, how should one arrange different IP blocks and chiplets? This project seeks to develop objective functions that comprehend power, performance, area, reliability and cost, along with techniques to handle both continuously valued and categorical design parameters.

  • Project PIs: Madhavan Swaminathan & Elyse Rosenbaum
  • Project Timeline: Summer 2021 – July 31, 2022

Invertible Neural Networks for Inverse System Modeling, Design and Identification

For the present-day high-speed electronics system and subsystem designs, the design spaces are huge and of a mixed nature, making design identification and tuning, a highly time and compute intensive and often heuristic process. In this research project, the uniqueness and elegance of Invertible Neural Networks is being used to identify non-intuitive designs that meet the electrical spec and offer the designer a set of feasible design options to choose from. Ongoing work encompasses designing the INN, tuning the hyperparameters and setting it up to work for spec-based envelopes in output spaces for two separate applications of signal and power integrity. 

  • Project PI: Madhavan Swaminathan
  • Project Timeline: Jan 1, 2021 – July 31, 2022