University of Illinois at Urbana-Champaign
Coordinated Science Laboratory
Center for Advanced Electronics Through Machine Learning

Current Research Projects

Machine Learning Method for Inverse Design and Optimization of High-Speed Links

Our plan is to develop a machine learning-driven method for solving inverse and optimization problems in hardware design. We will leverage forward surrogate models developed in earlier CAEML research, along with additional training and dimensionality reduction methods to synthesize candidate designs that meet specified performance objects, speeding up the design process

  • Project PI: Xu Chen and Andreas Cangellaris
  • Project Timeline: Jan 1, 2021 – July 31, 2023

High Dimensional Optimization and Inverse Methods for Electronic Design

This project aims to use high dimensional optimization approaches in electronic system design. Techniques that will be considered include surrogate modeling, Bayesian optimization, and inverse neural networks.

  • Project PI: Paul Franzon, Brian Floyd and Dror Baron
  • Project Timeline: Jan 1, 2021 – July 31, 2023

GAN generated models for Signal Integrity, Thermal Modeling, Etc.

This project will use conditional GANs to model drivers and receivers and to support thermal modeling.

  • Project PI: Paul Franzon, Chau -Wai Wu, Tainfu Wu, Rhett Davis & Dror Baron
  • Project Timeline: Jan 1, 2021 – July 31, 2023

ML-Based Security Analysis of Homomorphic Encryption Side-Channels

This project explores implementation security issues of homomorphic encryption solutions. Specifically, the project aims exposing the first side-channel vulnerabilities of edge devices executing homomorphic encryption/decryption and integrating the side-channel analysis into standard EDA flows. Machine learning techniques will enable automating the proposed work and achieving effective attacks that can outperform conventional ones

  • Project PI: Aydin Aysu and Paul Franzon
  • Project Timeline: Jan 1, 2021 – July 31, 2023

Reliability-Driven Thermal Optimization of 2.5D and 3D Packaging Architectures

There has been rapid development of new packaging technologies to support 2.5/3D heterogeneous integration. To fully exploit those capabilities without sacrificing time-to-market requires the development of a multi-objective optimization framework that can answer the following questions: What are the optimum architecture and materials from a set of possible choices? Given a fixed architecture, how should one arrange different IP blocks and chiplets? This project seeks to develop objective functions that comprehend power, performance, area, reliability and cost, along with techniques to handle both continuously valued and categorical design parameters.

  • Project PIs: Madhavan Swaminathan & Elyse Rosenbaum
  • Project Timeline: Summer 2021 – July 31, 2023

Invertible Neural Networks for Inverse System Modeling, Design and Identification

For the present-day high-speed electronics system and subsystem designs, the design spaces are huge and of a mixed nature, making design identification and tuning, a highly time and compute intensive and often heuristic process. In this research project, the uniqueness and elegance of Invertible Neural Networks is being used to identify non-intuitive designs that meet the electrical spec and offer the designer a set of feasible design options to choose from. Ongoing work encompasses designing the INN, tuning the hyperparameters and setting it up to work for spec-based envelopes in output spaces for two separate applications of signal and power integrity. 

  • Project PI: Madhavan Swaminathan
  • Project Timeline: Jan 1, 2021 – July 31, 2023

Security Analysis of XG Boost Ransomware Detector through Side-Channel Attacks and/or Power Hammering Attacks

The proposed research will be conducted over three phases. Phase 1: Collect relevant datasets for different classification problems and devise an experimental setup to conduct experiments. Phase 2: Attacking FPGA with side-channel attacks to steal the model information and/or derange the FPGA by power-hammering attacks. Phase 3: Innovate techniques to defend against such attacks.  

  • Project PI: Paul Franzon & Aydin Aysu
  • Project Timeline: August 1, 2022 - July 31, 2023

IC Failures-In-Time (FIT) Rate Prediction. Part 1: MOL and BEOL Time Dependent Dielectric Breakdown

This project will demonstrate physics-integrated variational autoencoders that generate time-to-breakdown distributions of BEOL and MOL dielectrics with variable areas. The key impediment to a purely physics-based approach is that the underlying distribution of dielectric thicknesses is not known.

  • Project PI: Elyse Rosenbaum
  • Project Timeline: August 1, 2022 - July 31, 2023

Quantifying Privacy in Distributed Learning for Integrated Circuit Design

This project seeks to promote the sharing of proprietary data in collaborative databases by experimentally quantifying the privacy of distributed learning on an integrated circuit design application. This project will set up a distributed database with an ML-EDA application, show that deterministic privacy when granting access can be guaranteed by an approach called View-Verified Data Exchange, and show that differential privacy in Federated Learning can be guaranteed by a model-poisoning defense.

  • Project PIs: Rhett Davis, Rada Chirkova, Bo Li
  • Project Timeline: January 1, 2023 - December 31, 2023

Physical Design Parameter Optimization (PDPO) Using Reinforcement Learning

Given a synthesized netlist, PPA targets, a target technology, and the list of PD tool parameters, the objective of this project is to (1) tune the parameters automatically using Reinforcement Learning (RL) models so that the final GDS layouts meet the PPA goals, and (2) minimize the time needed to train the RL model.

  • Project PI: Sung Kyu Lim
  • Project Timeline: January 1, 2023 - December 31, 2023