Selected Research Results
Circuit aging simulation may be performed with RNN models of library cells or IP blocks rather than transistor level models (labeled RelXpert in figure). The continuous time RNN is implemented in Verilog-A.
Reference: E. Rosenbaum, J. Xiong, A. Yang, Z. Chen and M. Raginsky, “Machine learning for circuit aging simulation,” 2020 IEDM. https://doi.org/10.1109/IEDM13553.2020.9371931
Comparison of cross-device attacks on Frodo and NewHope post-quantum cryptography algorithms. 1D-CNN+Reg follows the approach of Kim et al. DS indicates that a downsampled power trace was used to train/evaluate the model.
Reference: Kashyap, Priyank, Furkan Aydin, Seetal Potluri, Paul Franzon, and Aydin Aysu. “2Deep: Enhancing Side-Channel Attacks on Lattice-Based Key-Exchange via 2D Deep Learning.” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (2020), doi: 10.1109/TCAD.2020.3038701.
The Candidate algorithm for analog circuit optimization outperforms human designers and Bayesian optimization.
Reference: Y. Wang and P. D. Franzon, “RFIC IP Redesign and Reuse Through Surrogate Based Machine Learning Method,” 2018 IEEE MTT-S International Conference on Numerical Electromagnetic and Multiphysics Modeling and Optimization (NEMO), Reykjavik, Iceland, 2018, pp. 1-4. doi: 10.1109/NEMO.2018.8503446
ML-based classification for power side-channel attack on the SEAL Homomorphic Encryption Library: (a) An example of averaged power trace corresponds to an addition operation in the butterfly operation, (b) principal component analysis (PCA) scores for power traces with the samples from 200 to 350 corresponds to addition operations, (c) PCA scores for power traces with samples from 200 to 350 corresponds to subtraction operations.
Reference: Furkan Aydin, Aydin Aysu "Exposing Side-Channel Leakage of SEAL Homomorphic Encryption Library", Attacks and Solutions in Hardware Security (ASHES) 2022, Nov, 2022,
Sufficient summary plot showing relationship between eye width and a 1-dimensional active variable reduced from a 16-dimensional problem.
Reference: H. Ma, E. -P. Li, A. C. Cangellaris and X. Chen, “High-Speed Link Design Optimization Using Machine Learning SVR-AS Method,” 2020 IEEE 29th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), 2020, pp. 1-3, doi: 10.1109/EPEPS48591.2020.9231368.
Causal feature selection allows for HDD failure prediction with a reduced set of sensor data.
Reference: A. Yang, A. Ghassami, M. Raginsky, N. Kiyavash and E. Rosenbaum, “Model-Augmented Conditional Mutual Information Estimation for Feature Selection,” 2020 UAI, http://proceedings.mlr.press/v124/yang20b.html
Modeling of Irregular Shaped Power Distribution Planes Using Invertible Neural Network
Clock tree synthesis (CTS) using a generative adversarial network (GAN) outperforms commercial tools.
Reference: Y.-C. Lu, J. Lee, A. Agnesina, K. Samadi and S. K. Lim, “GAN-CTS: A Generative Adversarial Framework for Clock Tree Prediction and Optimization,” 2019 ICCAD, doi: 10.1109/ICCAD45719.2019.8942063
Replace a receiver model with an easy to build NNARMAX model.
Reference: B. Li, B. Jiao, M. Huang, R. Mayder and P. Franzon, “Improved System Identification Modeling for High-speed Receiver,” 2019 IEEE 28th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), Montreal, QC, Canada, 2019, pp. 1-3.
We compare state-of-the-art inverse design strategies for a high-speed channel. Generative models considered provide rich posterior probability distributions of channel parameters when conditioned on a target specification of eye-quality.
Reference: O. W. Bhatti et al., "Comparison of Invertible Architectures for High Speed Channel Design," 2021 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS), 2021, pp. 1-3, doi: 10.1109/EDAPS53774.2021.9657014.